ARM Accredited engineer: EN0-001

Assume a multicore processor with coherency management based on the MESI protocol. When a core changes the contents of a shared cache line, what is the final status of that line in the local cache?

A. Modified

B. Exclusive

C. Shared

D. Invalid

Many ARM cores provide two instruction sets, ARM and Thumb. Which THREE of the following statements apply to the Thumb instruction set implemented for the ARMv7-A architecture? (Choose three)

A. Thumb is a hybrid 16/32-bit instruction set

B. No Thumb instructions can be conditionally executed

C. Thumb code is always slower than the equivalent ARM code

D. Some routines take more instructions in Thumb code than in the equivalent ARM code

E. The Thumb instruction set can access the Advanced SIMD "NEON" instructions

F. Thumb code is always more power-efficient than equivalent ARM code

A development board is supplied with a Board Support Package (BSP) for a particular operating system. Which TWO of these items would you expect to find in the BSP? (Choose two)

A. Power supply and electrical cables

B. Debugging hardware and software solution

C. System on chip peripheral driver source code

D. Boundary scan protocol definition

E. Boot code for board-specific devices